(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing silicon pits in the active region in the fabrication of integrated circuits.
(2) Description of the Prior Art
As device sizes shrink into the sub-micron and sub-half-micron regime, it has become necessary to use a combination of polysilicon and refractory metal suicides as the material for gate electrodes and interconnection lines because of their reduced resistivity. It is also essential to keep the active regions as free from defects as possible. Pitting of the silicon in the active areas can cause junction leakage and low yields. FIG. 1 illustrates a partially completed integrated circuit device in which formed on a semiconductor substrate 10. A gate oxide 14 is grown on the substrate and overlaid with a polysilicon layer 16. Silicide layer 18 is deposited over the polysilicon layer and a tetraethoxysilane (TEOS) oxide layer 20 overlies the silicide layer as a hard mask. A barrier and antireflective coating (BARC) layer 22 is coated over the TEOS oxide layer 20 to underlay the photoresist mask 24.
Pinhole 25 forms in the BARC layer due to spin speed. As the BARC and hard mask layers 22 and 20 are etched to form the hard mask, as shown by dotted lines in FIG. 1, the portion of the layers underlying the pinhole 25 etches faster than the other portions of the layers resulting in a pit 27 in the silicide layer 18, as shown in FIG. 2. This pit may penetrate about 300 Angstroms into the silicide layer. When the polysilicon and silicide layers 16 and 18 are patterned to form a gate electrode, as illustrated by the dotted lines in FIG. 2, a pit is formed in the silicon underlying the silicide pit 27. Pitting of the silicon in the active areas can cause junction leakage and low yields.
Co-pending U.S. patent applications Ser. Nos. 09/004,188 to C. M. Yang et al and 09/004,190 to C. M. Yang et al, both filed on Jan. 8, 1998, teach different methods of preventing silicon pits in the active region by eliminating voids at the silicide/polysilicon interface. U.S. Pat. No. 5,710,076 to Dai et al teaches a two-step etching process in which the BARC and photoresist layers are etched using O.sub.2 /CHF.sub.3 /Ar, followed by an oxide etch using CHF.sub.3 /CF.sub.4 /Ar with a selectivity of oxide to BARC of 10:3. The use of CHF.sub.3 and CF.sub.4 as oxide etchants is disclosed in the book, ULSI Technology by C. Y. Chang and S. M. Sze, McGraw-Hill Company, NY, N.Y., C. 1997, pp. 353-354.